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INTEGRATED CIRCUITS
DATA SHEET
SAA7102; SAA7103 Digital video encoder
Product specification Supersedes data of 2001 Sep 25 File under Integrated Circuits, IC22 2002 Feb 18
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 8 8.1 8.2 9 10 11 11.1 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC Timing generator I2C-bus interface Programming the SAA7102; SAA7103 Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS Teletext timing 14.2 14.3 14.4 14.5 15 16 17 18 12 12.1 12.2 13 14 14.1
SAA7102; SAA7103
APPLICATION INFORMATION Analog output voltages Suggestions for a board layout PACKAGE OUTLINES SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2002 Feb 18
2
Philips Semiconductors
Product specification
Digital video encoder
1 FEATURES
SAA7102; SAA7103
* Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC * 27 MHz crystal-stable subcarrier generation * Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip or from external source * Up to 800 x 600 graphics data at 60 Hz or 50 Hz with programmable underscan range * Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) (signals in parenthesis are optional); all at 10-bit resolution * Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling * Downscaling from 1 : 1 to 1 : 2 and up to 20% upscaling * Optional interlaced CB-Y-CR input Digital Versatile Disk (DVD) * Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 45 MHz) * 3 x 256 bytes RGB Look-Up Table (LUT) * Support for hardware cursor * Programmable border colour of underscan area * On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) * Optional support of various Vertical Blanking Interval (VBI) data insertion * Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this applies to SAA7102 only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. * Power-save modes * Joint Test Action Group (JTAG) boundary scan test * Monolithic CMOS 3.3 V device, 5 V tolerant I/Os * QFP44 and BGA156 packages * Same footprint as SAA7108E; SAA7109E. 2 GENERAL DESCRIPTION
The SAA7102; SAA7103 is used to encode PC graphics data at maximum 800 x 600 resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and interlacer ensures properly sized and flicker-free TV display as CVBS or S-video output. Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 800 x 600 resolution/60 Hz (PIXCLK < 45 MHz). The device includes a sync/clock generator and on-chip DACs.
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7102E SAA7103E SAA7102H SAA7103H 4 QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILElf(DAC) DLElf(DAC) Tamb PARAMETER analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog CVBS output signal voltage for a 100/100 colour bar at 75/2 load (peak-to-peak value) load resistance low frequency integral linearity error of DACs low frequency differential linearity error of DACs ambient temperature MIN. 3.15 3.0 1 1 - - - - 0 QFP44 BGA156 DESCRIPTION plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm
SAA7102; SAA7103
VERSION SOT472-1 SOT307-2
plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
TYP. 3.3 3.3 110 70 1.23 37.5 - - -
MAX. 3.45 3.6 140 90 - - 3 1 70 V V
UNIT
mA mA V LSB LSB C
TTL compatible
2002 Feb 18
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VDDD1 10 4 to 1, 44 to 41, 16 to 19 VSSA1 VDDA2 VDDD2 RSET VSSD1 VSSD2 VDDA1 DUMP 9 40 39 36 29 33 32 31 TRST TDI 38 37 TCK 8 7 TDO TMS 6 PD11 to PD0 INPUT FORMATTER RGB LUT (OR BYPASS) CURSOR INSERTION RGB TO Y-CB-CR MATRIX (OR BYPASS) PIXCLKI 15 DECIMATOR 4 : 4 : 4 to 4 : 2 : 2 (OR BYPASS) HORIZONTAL SCALER VERTICAL SCALER AND ANTI-FLICKER FILTER FIFO 30 BORDER GENERATOR VIDEO ENCODER TRIPLE DAC 28 27 26 PIXCLKO 20 CGC LOW-PASS OSCILLATOR/ DTO TIMING GENERATOR I2C-BUS CONTROL 25
handbook, full pagewidth
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Philips Semiconductors
Digital video encoder Digital video encoder
BLOCK DIAGRAM
5 5
SAA7102H SAA7103H
23 35 XTALI TTX_SRES 27 MHz 34 XTAL VSVGC FSVGC HSVGC SDA SCL TTXRQ_XCLKO2 RESET 13 14 21 22 24 12 11 5 CBO
BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C HSM_CSYNC VSM
MHB963
SAA7102; SAA7103 SAA7102; SAA7103
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital video encoder
6 PINNING SYMBOL PD8 PD9 PD10 PD11 RESET TMS TDO TCK VSSD1 VDDD1 SCL SDA FSVGC VSVGC PIXCLKI PD3 PD2 PD1 PD0 PIXCLKO CBO HSVGC TTX_SRES TTXRQ_XCLKO2 VSM HSM_CSYNC RED_CR_C GREEN_VBS_CVBS VDDA1 BLUE_CB_CVBS PIN TYPE(1) BGA156 QFP44 B2 B1 C2 C1 D2 D3 D1 E1 E4 F4 E2 G2 G1 F1 F2 F3 H1 H2 H3 G4 G3 E3 C3 C4 D7 D8 C8 C7 A10, B9, C9, D9 C6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I I I I I I O I S S I I/O I/O I/O I I I I I O O I/O I O O O O O S O PIN
SAA7102; SAA7103
DESCRIPTION see Tables 25 to 30 for pin assignment see Tables 25 to 30 for pin assignment see Tables 25 to 30 for pin assignment see Tables 25 to 30 for pin assignment reset input; active LOW test mode select input for Boundary Scan Test (BST); note 2 test data output for BST; note 2 test clock input for BST; note 2 digital ground 1 (peripheral cells) digital supply voltage 1 (3.3 V, peripheral cells) I2C-bus serial clock input I2C-bus serial data input/output frame synchronization output to Video Graphics Controller (VGC) (optional input); note 3 vertical synchronization output to VGC (optional input); note 3 pixel clock input (looped through) MSB - 4 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment MSB - 5 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment MSB - 6 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment MSB - 7 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment pixel clock output to VGC composite blanking output to VGC; active LOW; note 3 horizontal synchronization output to VGC (optional input); note 3 teletext input or sync reset input teletext request output or 13.5 MHz clock output of the crystal oscillator; note 3 vertical synchronization output to monitor (non-interlaced auxiliary RGB) horizontal synchronization output to monitor (non-interlaced auxiliary RGB) or composite sync for RGB-SCART analog output of RED or CR or C signal analog output of GREEN or VBS or CVBS signal analog supply voltage 1 (3.3 V for DACs) analog output of BLUE or CB or CVBS signal
2002 Feb 18
6
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
SYMBOL RSET DUMP VSSA1 XTALO XTALI VDDA2 TRST TDI VSSD2 VDDD2 PD4 PD5 PD6 PD7 Notes
PIN (1) BGA156 QFP44 TYPE A9 A7, B7 A8, B8 A6 A5 B6, D6 A4 B5 C5, D5 D4 A3 B3 B4 A2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 O O S O I S I I S S I I I I
PIN
DESCRIPTION DAC reference pin; connected via 1 k resistor to analog ground (do not use capacitor in parallel with 1 k resistor) DAC reference pin; connected via 12 resistor to analog ground analog ground 1 crystal oscillator output crystal oscillator input analog supply voltage 2 (3.3 V for DACs and oscillator) test reset input for BST; active LOW; notes 2, 4 and 5 test data input for BST; note 2 digital ground 2 digital supply voltage 2 (3.3 V, core) MSB - 3 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment MSB - 2 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment MSB - 1 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment MSB with CB-Y-CR 4 : 2 : 2; see Tables 25 to 30 for pin assignment
1. Pin type: I = input, O = output, S = supply. 2. In accordance with the "IEEE1149.1" standard the pins TDI, TMS, TCK and TRST are input pins with an internal pull-up resistor and TDO is a 3-state output pin. 3. Pins FSVGC, VSVFC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1 4. For board design without boundary scan implementation connect TRST to ground. 5. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
Table 1 1 A B PD9 Pin assignment SAA7102E; SAA7103E (top view) 2 PD7 PD8 PD10 3 PD4 PD5 4 TRST PD6 5 6 7 8 9 10
SAA7102; SAA7103
11
12
13
14
XTALI XTALO DUMP TDI VDDA2 DUMP
VSSA1 RSET VDDA1 VSSA1 VDDA1
C PD11
TTX_ TTXRQ_ VSSD2 BLUE_ GREEN_ RED_ VDDA1 SRES XCLKO2 CB_ VBS_ CR_ CVBS CVBS C TMS VDDD2 VSSD2 VDDA2 VSM HSM_ VDDA1 CSYNC
D
TDO RESET
E
TCK
SCL
HSVGC VSSD1 VDDD1
F VSVGCPIXCLKI PD3 G FSVGC SDA H J K L M N P PD2 PD1
CBO PIXCLKO PD0
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
MHB907
handbook, halfpage
P N M L K J H G F E D C B A
SAA7102E SAA7103E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig.2 Pin configuration (SAA7102E; SAA7103E).
40 VDDD2
36 VDDA2
39 VSSD2
PD8 PD9 PD10 PD11 RESET TMS TDO TCK VSSD1
1 2 3 4 5 6 7 8 9
35 XTALI
37 TRST
handbook, full pagewidth
34 XTALO
44 PD7
43 PD6
42 PD5
41 PD4
38 TDI
33 VSSA1 32 DUMP 31 RSET 30 BLUE_CB_CVBS 29 VDDA1
SAA7102H SAA7103H
28 GREEN_VBS_CVBS 27 RED_CR_C 26 HSM_CSYNC 25 VSM 24 TTXRQ_XCLKO2 23 TTX_SRES
VDDD1 10 SCL 11
SDA 12
FSVGC 13
VSVGC 14
PIXCLKI 15
PD3 16
PD2 17
PD1 18
PD0 19
PIXCLKO 20
CBO 21
HSVGC 22
MHB908
Fig.3 Pin configuration (SAA7102H; SAA7103H).
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
7 FUNCTIONAL DESCRIPTION
SAA7102; SAA7103
For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 4 to 9. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals. The 8-bit multiplexed CB-Y-CR formats are "ITU-R BT.656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 25 to 30. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. The SAA7102; SAA7103 synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains Closed Caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Fig.14). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters such as: * Black and blanking level control * Colour subcarrier frequency * Variable burst amplitude etc.
The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported. The SAA7102; SAA7103 can be directly connected to a PC video graphics controller with a maximum resolution of 800 x 600 at a 50 or 60 Hz frame rate. A programmable scaler scales the computer graphics picture so that it will fit into a standard TV screen with an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 25 to 30. A complete 3 x 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port PD (Pixel Data) or via the I2C-bus. The SAA7102; SAA7103 supports a 32 x 32 x 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus. It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7102; SAA7103 can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 : 2 : 2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "ITU-R BT.470-3".
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
7.1 Reset conditions
SAA7102; SAA7103
If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. 7.3 RGB LUT
To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2. Table 2 Strapping pins PIN FSVGC TIED LOW PRESET NTSC M encoding, PIXCLK fits to 640 x 480 graphics input
The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel. The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 x 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on. 7.4 Cursor insertion
HIGH PAL B/G encoding, PIXCLK fits to 640 x 480 graphics input VSVGC LOW 4 : 2 : 2 Y-CB-CR graphics input (format 0)
HIGH 4 : 4 : 4 RGB graphics input (format 3) CBO LOW input demultiplex phase: LSB = LOW
A 32 x 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write access to specific registers or in the pixel data input through the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line. The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the `cursor colours' can be programmed in separate registers. The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner. Table 3 D7 D1 Layout of a byte in the cursor bit map D6 D0 D5 D1 D4 D0 D3 D1 D2 D0 D1 pixel n D1 D0 D0
HIGH input demultiplex phase: LSB = HIGH HSVGC LOW input demultiplex phase: MSB = LOW
HIGH input demultiplex phase: MSB = HIGH TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and HSVGC are inputs, internal colour bar is active)
HIGH master (FSVGC, VSVGC and HSVGC are outputs) 7.2 Input formatter
pixel n + 3
pixel n + 2
pixel n + 1
The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream. When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits EDGE1 and EDGE2 for correct operation. 2002 Feb 18 11
For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the `hot spot', the other register controls the insertion position. The hot spot is the `tip' of the pointer arrow.
Philips Semiconductors
Product specification
Digital video encoder
It can have any position in the bit map. The actual position register describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution. Table 4 BYTE 0 1 2 Cursor bit map D7 D6 D5 D4 D3 D2 D1 D0
SAA7102; SAA7103
The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC. 7.6 Horizontal scaler
The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically. The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. If the SAA7102; SAA7103 input data is in accordance with "ITU-R BT.656", the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output. 7.7 Vertical scaler and anti-flicker filter
row 0 column 3 row 0 column 7 row 0 column 11 ... row 0 column 27 row 0 column 31 ... row 31 column 27 row 31 column 31
row 0 column 2 row 0 column 6 row 0 column 10 ... row 0 column 26 row 0 column 30 ... row 31 column 26 row 31 column 30
row 0 column 1 row 0 column 5 row 0 column 9 ... row 0 column 25 row 0 column 29 ... row 31 column 25 row 31 column 29
row 0 column 0 row 0 column 4 row 0 column 8 ... row 0 column 24 row 0 column 28 ... row 31 column 24 row 31 column 28
... 6
7
... 254
The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. The circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095 switches it off; see Table 95. The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0. Due to the re-interlacing, the circuit can perform upscaling. The maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in Section 7.17.
255
Table 5
Cursor modes CURSOR MODE CMODE = 0 first cursor colour transparent inverted input CMODE = 1 first cursor colour transparent auxiliary cursor colour
CURSOR PATTERN 00 01 10 11
second cursor colour second cursor colour
7.5
RGB Y-CB-CR matrix
RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR colour space in this block. The colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. 2002 Feb 18 12
Philips Semiconductors
Product specification
Digital video encoder
7.8 FIFO
SAA7102; SAA7103
Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7102 only. To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 6 and 7. Appropriate transients at start/end of active video and for synchronization pulses are ensured. Chrominance is modified in gain (programmable separately for CB and CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 4 and 5. The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. The numeric ratio between the Y and C outputs is in accordance with the standards. 7.12.2 TELETEXT INSERTION AND ENCODING (NOT
SIMULTANEOUSLY WITH REAL-TIME CONTROL)
The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access. In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor. It is suggested to refer to Tables 6 to 23 for some representative combinations. 7.9 Border generator
When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint. 7.10 Oscillator and Discrete Time Oscillator (DTO)
The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 18 and 44 MHz. 7.11 Low-pass Clock Generation Circuit (CGC)
This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies. 7.12 7.12.1 Encoder VIDEO PATH
The encoder generates luminance and colour subcarrier output signals from the Y, CB and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals.
Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES.
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.14. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz. 7.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
SAA7102; SAA7103
The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 8 and 9. 7.14 Triple DAC
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of the conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75 ) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. If the SAA7102; SAA7103 is required to drive a second (auxiliary) VGA monitor, the DACs receive the signal directly from the cursor insertion block. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder. 7.15 Timing generator
Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. 7.12.4 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number in which data is to be encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 7.12.5 ANTI-TAPING (SAA7102 ONLY)
The synchronization of the SAA7102; SAA7103 is able to operate in two modes; slave mode and master mode. In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode. Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0.
For more information contact your nearest Philips Semiconductors sales office. 7.13 RGB processor
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed.
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7102; SAA7103. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits. In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed. The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 12 and 13): * The horizontal offset * The length of the active part of the line * The distance from active start to first expected data * The vertical offset separately for odd and even fields * The number of lines per input field. In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7102; SAA7103 will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 105. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0. 7.16 I2C-bus interface
SAA7102; SAA7103
The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is assigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address. The I2C-bus slave address is defined as 88H. 7.17 Programming the SAA7102; SAA7103
In order to program the SAA7102; SAA7103 it is first necessary to determine the input and output field timings. The timings are controlled by decoding binary counters that index the position in the current line and field respectively. In both cases, 0 means the start of the sync pulse. At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. Some variables are defined below: * InPix: the number of active pixels per input line * InPpl: the length of the entire input line in pixel clocks * InLin: the number of active lines per input field/frame * TPclk: the pixel clock period * OutPix: the number of active pixels per output line * OutLin: the number of active lines per output field * TXclk: the encoder clock period (37.037 ns). The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 72. ADWHS = 256 + 710 - OutPix (60 Hz); ADWHS = 284 + 702 - OutPix (50 Hz); ADWHE = ADWHS + OutPix x 2 (all frequencies) For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 78. 240 - OutLin FAL = 19 + -------------------------------- (60 Hz); 2 287 - OutLin FAL = 23 + -------------------------------- (50 Hz); 2 LAL = FAL + OutLin (all frequencies)
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and read, except two read only status bytes.
2002 Feb 18
15
Philips Semiconductors
Product specification
Digital video encoder
Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10%, giving approximately 640 output pixels per line. The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses. The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function. Thus: 262.5 x 1716 x TXclk TPclk = --------------------------------------------------------------------------------------- (60 Hz) InLin + 2 InPpl x integer --------------------- x 262.5 OutLin 312.5 x 1728 x TXclk TPclk = --------------------------------------------------------------------------------------- (50 Hz) InLin + 2 InPpl x integer --------------------- x 312.5 OutLin TXclk 21 and for the pixel clock generator PCL = -------------- x 2 TPclk (all frequencies); see Table 81. The input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: FAL x 1716 x TXclk YOFS = --------------------------------------------------- - 2 (60 Hz) InPpl x TPclk FAL x 1728 x TXclk YOFS = --------------------------------------------------- - 2 (50 Hz) InPpl x TPclk In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down. Once the timings are known the scaler can be programmed. XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX HLEN is fulfilled. Values given by the VESA display timings are preferred. OutPix InPix HLEN = InPpl - 1 XPIX = ------------ XINC = ----------------- x 4096 InPix 2 XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. YPIX = InLin
SAA7102; SAA7103
YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. OutLin YSKIP YINC = --------------------- x 1 + ---------------- x 4096 InLin + 2 4095 YINC YIWGTO = ------------- + 2048 2 YINC - YSKIP YIWGTE = ------------------------------------2 When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. Due to the limited amount of memory it is not possible to get valid vertical scaler settings only from the formulae above. In some cases it is necessary to adjust the vertical offsets or the scaler increment to get valid settings. Tables 6 to 23 show verified settings. They are organised in the following way: The tables are separate for the standard to be encoded, the input resolution and three different anti-flicker filter settings. Each table contains 5 vertical sizes with 5 different offsets. They are intended to be selected according to the current TV set. The corresponding horizontal resolutions of 640 pixels give proper aspect ratios. They can be adjusted according to the formulae above. The next line gives a minimum size intended to fit on the screen under all circumstances. The corresponding horizontal resolution is 620 pixels. Overscan is only possible with an input resolution of 800 x 600 pixels. Where possible, the corresponding settings are given on the last lines of the tables.
2002 Feb 18
16
Philips Semiconductors
Product specification
Digital video encoder
7.18 Input levels and formats
SAA7102; SAA7103
The SAA7102; SAA7103 accepts digital Y, CB, CR or RGB data with levels (digital codes) in accordance with "ITU-R BT.601"; see Table 24. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The RGB, respectively CR-Y-CB path features an individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. Table 6 Y scaler programming at NTSC, input frame size: 640 x 400, full anti-flicker filter OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
TV LINE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 1851099 1851099 1851099 1851099 1851099 1836201 1836201 1836201 1836201 1836201 1817578 1817578 1817578 1817578 1817578 1802680 1802680 1802680 1802680 1802680 1784057 1784057 1784057 1784057 1784057 2163 2163 2163 2163 2163 2181 2181 2181 2181 2181 2202 2202 2202 2202 2202 2222 2222 2222 2222 2222 2245 2245 2245 2245 2245 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52 56 60 63 67 50 54 57 61 65 47 51 55 58 62 45 49 53 56 60 43 46 50 54 57 52 56 60 63 67 50 54 57 61 65 47 51 55 58 62 45 49 53 56 60 43 46 50 54 57 3128 3128 3128 3128 3128 3138 3138 3138 3138 3138 3148 3148 3148 3148 3148 3158 3158 3158 3158 3158 3168 3168 3168 3168 3168 1080 1080 1080 1080 1080 1090 1090 1090 1090 1090 1100 1100 1100 1100 1100 1110 1110 1110 1110 1110 1120 1120 1120 1120 1120
Overscan (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 204 0 37 241 1925590 2079 0 70 70 3087 1039
2002 Feb 18
17
Philips Semiconductors
Product specification
Digital video encoder
Table 7
SAA7102; SAA7103
Y scaler programming at NTSC, input frame size: 640 x 400, half anti-flicker filter OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
TV LINE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 1851099 1851099 1851099 1851099 1851099 1836201 1836201 1836201 1836201 1836201 1817578 1817578 1817578 1817578 1817578 1802680 1802680 1802680 1802680 1802680 1784057 1784057 1784057 1784057 1784057 3123 3123 3123 3123 3123 3135 3135 3135 3135 3135 3145 3145 3145 3145 3145 3155 3155 3155 3155 3155 3165 3165 3165 3165 3165 1820 1820 1820 1820 1820 1790 1790 1790 1790 1790 1750 1750 1750 1750 1750 1720 1720 1720 1720 1720 1680 1680 1680 1680 1680 52 56 60 64 67 50 54 58 61 65 48 51 55 59 63 45 49 53 56 60 43 47 50 54 58 52 56 60 64 67 50 54 58 61 65 48 51 55 59 63 45 49 53 56 60 43 47 50 54 58 3668 3668 3668 3668 3668 3683 3683 3683 3683 3683 3698 3698 3698 3698 3698 3714 3714 3714 3714 3714 3729 3729 3729 3729 3729 596 596 596 596 596 611 611 611 611 611 626 626 626 626 626 642 642 642 642 642 657 657 657 657 657
Full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 204 0 37 241 1925590 3087 1980 70 70 3589 551
2002 Feb 18
18
Philips Semiconductors
Product specification
Digital video encoder
Table 8
SAA7102; SAA7103
Y scaler programming at NTSC, input frame size: 640 x 400, no anti-flicker filter OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
TV LINE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 1851099 1851099 1851099 1851099 1851099 1836201 1836201 1836201 1836201 1836201 1817578 1817578 1817578 1817578 1817578 1802680 1802680 1802680 1802680 1802680 1784057 1784057 1784057 1784057 1784057 4094 4094 4094 4094 4094 4090 4090 4090 4088 4088 4093 4093 4093 4093 4093 4092 4092 4092 4092 4092 4090 4090 4090 4090 4090 3655 3655 3655 3655 3655 3580 3580 3580 3580 3580 3510 3510 3510 3510 3510 3445 3445 3445 3445 3445 3370 3370 3370 3370 3370 52 56 60 64 68 50 54 58 61 65 48 52 55 59 63 46 49 53 57 60 43 47 50 54 58 52 56 60 64 68 50 54 58 61 65 48 52 55 59 63 46 49 53 57 60 43 47 50 54 58 4092 4092 4092 4092 4092 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4092 4092 4092 4092 4092 4091 4091 4091 4091 4091 216 216 216 216 216 253 253 253 253 253 288 288 288 288 288 322 322 322 322 322 358 358 358 358 358
Full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 204 0 37 241 1925590 4087 3950 70 70 4089 66
2002 Feb 18
19
Philips Semiconductors
Product specification
Digital video encoder
Table 9
SAA7102; SAA7103
Y scaler programming at NTSC, input frame size: 640 x 480, full anti-flicker filter OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
TV LINE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 2219829 2219829 2219829 2219829 2219829 2201206 2201206 2201206 2201206 2201206 2178859 2178859 2178859 2178859 2178859 2160236 2160236 2160236 2160236 2160236 2141613 2141613 2141613 2141613 2141613 1804 1804 1804 1804 1804 1819 1819 1819 1819 1819 1836 1836 1836 1836 1836 1853 1853 1853 1853 1853 1870 1870 1870 1870 1870 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 67 72 77 81 60 65 69 73 78 57 61 66 70 75 54 59 63 68 72 52 56 61 65 69 63 67 72 77 81 60 65 69 73 78 57 61 66 70 75 54 59 63 68 72 52 56 61 65 69 2948 2948 2948 2948 2948 2957 2957 2957 2957 2957 2965 2965 2965 2965 2965 2974 2974 2974 2974 2974 2982 2982 2982 2982 2982 900 900 900 900 900 909 909 909 909 909 917 917 917 917 917 926 926 926 926 926 934 934 934 934 934
Full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 204 0 37 241 2309218 1734 0 84 84 2941 866
2002 Feb 18
20
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 10 Y scaler programming at NTSC, input frame size: 640 x 480, half anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 2219829 2219829 2219829 2219829 2219829 2201206 2201206 2201206 2201206 2201206 2178859 2178859 2178859 2178859 2178859 2160236 2160236 2160236 2160236 2160236 2141613 2141613 2141613 2141613 2141613 2704 2704 2704 2704 2704 2730 2730 2730 2730 2730 2756 2756 2756 2756 2756 2781 2781 2781 2781 2781 2807 2807 2807 2807 2807 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 63 67 72 77 81 60 65 69 74 78 57 62 66 71 75 55 59 63 68 72 52 57 61 65 70 63 67 72 77 81 60 65 69 74 78 57 62 66 71 75 55 59 63 68 72 52 57 61 65 70 3399 3399 3399 3399 3399 3412 3412 3412 3412 3412 3424 3424 3424 3424 3424 3437 3437 3437 3437 3437 3450 3450 3450 3450 3450 327 327 327 327 327 340 340 340 340 340 352 352 352 352 352 365 365 365 365 365 378 378 378 378 378
Full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 204 0 37 241 2309218 2602 2048 84 84 3348 276
2002 Feb 18
21
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 11 Y scaler programming at NTSC, input frame size: 640 x 480, no anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 2219829 2219829 2219829 2219829 2219829 2201206 2201206 2201206 2201206 2201206 2178859 2178859 2178859 2178859 2178859 2160236 2160236 2160236 2160236 2160236 2141613 2141613 2141613 2141613 2141613 3607 3607 3607 3607 3607 3639 3639 3639 3639 3639 3675 3675 3675 3675 3675 3709 3709 3709 3709 3709 3741 3741 3741 3741 3741 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 63 68 72 77 81 60 65 69 74 78 57 62 66 71 75 55 59 64 68 73 52 57 61 65 70 64 69 73 78 82 61 66 70 75 79 58 63 67 72 76 56 60 65 69 74 53 58 62 66 71 3849 3849 3849 3849 3849 3866 3866 3866 3866 3866 3883 3883 3883 3883 3883 3900 3900 3900 3900 3900 3917 3917 3917 3917 3917 3362 3362 3362 3362 3362 3413 3413 3413 3413 3413 3464 3464 3464 3464 3464 3515 3515 3515 3515 3515 3566 3566 3566 3566 3566
Full size (horizontal size: 710 pixels) 241 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 204 0 37 241 2309218 3471 4095 85 86 3781 3158
2002 Feb 18
22
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 12 Y scaler programming at NTSC, input frame size: 800 x 600, full anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 3551726 3551726 3551726 3551726 3551726 3518354 3518354 3518354 3518354 3518354 3484982 3484982 3484982 3484982 3484982 3451610 3451610 3451610 3451610 3451610 3423006 3423006 3423006 3423006 3423006 1443 1443 1443 1443 1443 1457 1457 1457 1457 1457 1470 1470 1470 1470 1470 1484 1484 1484 1484 1484 1497 1497 1497 1497 1497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 84 90 96 102 75 81 86 92 98 72 77 82 88 94 68 73 79 85 90 65 71 76 81 87 79 84 90 96 102 75 81 86 92 98 72 77 82 88 94 68 73 79 85 90 65 71 76 81 87 2769 2769 2769 2769 2769 2776 2776 2776 2776 2776 2782 2782 2782 2782 2782 2789 2789 2789 2789 2789 2796 2796 2796 2796 2796 721 721 721 721 721 728 728 728 728 728 734 734 734 734 734 741 741 741 741 741 748 748 748 748 748
Full size (horizontal size: 710 pixels) 241 0 18 259 3122659 1642 0 42 42 2867 819
Small size (horizontal size: 620 pixels) 204 0 37 241 3689981 1389 0 106 106 2742 694
2002 Feb 18
23
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 13 Y scaler programming at NTSC, input frame size: 800 x 600, half anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 3551726 3551726 3551726 3551726 3551726 3518354 3518354 3518354 3518354 3518354 3484982 3484982 3484982 3484982 3484982 3451610 3451610 3451610 3451610 3451610 3423006 3423006 3423006 3423006 3423006 2165 2165 2165 2165 2165 2185 2185 2185 2185 2185 2205 2205 2205 2205 2205 2226 2226 2226 2226 2226 2246 2246 2246 2246 2246 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 79 85 91 96 102 75 81 87 92 98 72 77 83 89 94 68 74 80 85 90 65 71 76 81 87 79 85 91 96 102 75 81 87 92 98 72 77 83 89 94 68 74 80 85 90 65 71 76 81 87 3129 3129 3129 3129 3129 3140 3140 3140 3140 3140 3150 3150 3150 3150 3150 3160 3160 3160 3160 3160 3170 3170 3170 3170 3170 57 57 57 57 57 68 68 68 68 68 78 78 78 78 78 88 88 88 88 88 98 98 98 98 98
Full size (horizontal size: 710 pixels) 241 0 18 259 3122659 2461 2048 42 42 3277 205
Small size (horizontal size: 620 pixels) 204 0 37 241 3689981 2083 2048 106 106 3089 17
2002 Feb 18
24
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 14 Y scaler programming at NTSC, input frame size: 800 x 600, no anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 212 212 212 212 214 214 214 214 214 216 216 216 216 216 218 218 218 218 218 220 220 220 220 220 29 31 33 35 37 28 30 32 34 36 27 29 31 33 35 26 28 30 32 34 25 27 29 31 33 241 243 245 247 249 242 244 246 248 250 243 245 247 249 251 244 246 248 250 252 245 247 249 251 253 3551726 3551726 3551726 3551726 3551726 3518354 3518354 3518354 3518354 3518354 3484982 3484982 3484982 3484982 3484982 3451610 3451610 3451610 3451610 3451610 3423006 3423006 3423006 3423006 3423006 2887 2887 2887 2887 2887 2912 2912 2912 2912 2912 2941 2941 2941 2941 2941 2969 2969 2969 2969 2969 2994 2994 2994 2994 2994 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 79 85 91 96 102 76 81 87 92 98 72 78 83 89 94 69 74 80 85 90 65 71 76 82 87 80 86 92 97 103 77 82 88 93 99 73 79 84 90 95 70 75 81 86 91 66 72 77 83 88 3490 3490 3490 3490 3490 3504 3504 3504 3504 3504 3517 3517 3517 3517 3517 3531 3531 3531 3531 3531 3544 3544 3544 3544 3544 2282 2282 2282 2282 2282 2323 2323 2323 2323 2323 2364 2364 2364 2364 2364 2405 2405 2405 2405 2405 2446 2446 2446 2446 2446
Full size (horizontal size: 710 pixels) 241 0 18 259 3122659 3282 4095 42 43 3687 2875
Small size (horizontal size: 620 pixels) 204 0 37 241 3689981 2778 4095 106 107 3436 2119
2002 Feb 18
25
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 15 Y scaler programming at PAL, input frame size: 640 x 400, full anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 1528590 1528590 1528590 1528590 1528590 1516163 1516163 1516163 1516163 1516163 1506842 1506842 1506842 1506842 1506842 1494414 1494414 1494414 1494414 1494414 1481987 1481987 1481987 1481987 1481987 2600 2602 2602 2602 2602 2621 2623 2623 2623 2623 2641 2641 2641 2641 2641 2661 2661 2661 2661 2661 2684 2684 2684 2684 2684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52 55 59 62 65 50 53 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 52 55 59 62 65 50 53 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 3347 3347 3347 3347 3347 3357 3357 3357 3357 3357 3367 3367 3367 3367 3367 3377 3377 3377 3377 3377 3387 3387 3387 3387 3387 1299 1299 1299 1299 1299 1309 1309 1309 1309 1309 1319 1319 1319 1319 1319 1329 1329 1329 1329 1329 1339 1339 1339 1339 1339
Full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 250 0 41 291 1559659 2549 0 63 63 3321 1273
2002 Feb 18
26
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 16 Y scaler programming at PAL, input frame size: 640 x 400, half anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 1528590 1528590 1528590 1528590 1528590 1516163 1516163 1516163 1516163 1516163 1506842 1506842 1506842 1506842 1506842 1494414 1494414 1494414 1494414 1494414 1481987 1481987 1481987 1481987 1481987 3346 3346 3346 3346 3346 3360 3360 3360 3360 3360 3362 3362 3362 3362 3362 3378 3378 3378 3378 3378 3384 3384 3384 3384 3384 1170 1170 1170 1170 1170 1150 1150 1150 1150 1150 1120 1120 1120 1120 1120 1100 1100 1100 1100 1100 1070 1070 1070 1070 1070 53 56 59 62 65 51 54 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 53 56 59 62 65 51 54 57 60 63 49 52 55 58 61 47 50 53 56 59 45 48 51 54 57 3996 3996 3996 3996 3996 4012 4012 4012 4012 4012 4070 4070 4070 4070 4070 4042 4042 4042 4042 4042 4057 4057 4057 4057 4057 924 924 924 924 924 940 940 940 940 940 998 998 998 998 998 970 970 970 970 970 985 985 985 985 985
Full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 250 0 41 291 1559659 3322 1240 63 63 3707 1039
2002 Feb 18
27
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 17 Y scaler programming at PAL, input frame size: 640 x 400, no anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 42 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 301 293 295 297 299 301 294 296 298 300 302 1528590 1528590 1528590 1528590 1528590 1516163 1516163 1516163 1516163 1516163 1506842 1506842 1506842 1506842 1506842 1494414 1494414 1494414 1494414 1494414 1481987 1481987 1481987 1481987 1481987 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4093 4093 4093 4091 4091 4094 4094 4094 4093 4093 4092 4092 4092 4092 4092 2350 2350 2350 2350 2350 2300 2300 2300 2300 2300 2250 2250 2250 2250 2250 2200 2200 2200 2200 2200 2150 2150 2150 2150 2150 53 56 59 62 65 51 54 57 60 63 49 52 55 58 63 47 50 53 56 59 45 48 51 54 57 53 56 59 62 65 51 54 57 60 63 49 52 55 58 63 47 50 53 56 59 45 48 51 54 57 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4092 4091 4091 4091 4091 4091 869 869 869 869 869 894 894 894 894 894 919 919 919 919 919 944 944 944 944 944 968 968 968 968 968
Full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 250 0 41 291 1559659 4087 2470 63 63 4089 806
2002 Feb 18
28
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 18 Y scaler programming at PAL, input frame size: 640 x 480, full anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 1833066 1833066 1833066 1833066 1833066 1820638 1820638 1820638 1820638 1820638 1805104 1805104 1805104 1805104 1805104 1792676 1792676 1792676 1792676 1792676 1777142 1777142 1777142 1777142 1777142 2168 2168 2168 2168 2168 2185 2185 2185 2185 2185 2202 2202 2202 2204 2202 2219 2219 2219 2219 2219 2238 2238 2238 2238 2238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 67 71 74 78 61 65 69 72 76 58 62 66 70 73 56 60 64 67 71 54 58 61 65 69 63 67 71 74 78 61 65 69 72 76 58 62 66 70 73 56 60 64 67 71 54 58 61 65 69 3131 3131 3131 3131 3131 3139 3139 3139 3139 3139 3148 3148 3148 3148 3148 3156 3156 3156 3156 3156 3165 3165 3165 3165 3165 1083 1083 1083 1083 1083 1091 1091 1091 1091 1091 1100 1100 1100 1100 1100 1108 1108 1108 1108 1108 1117 1117 1117 1117 1117
Full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 250 0 41 291 1870348 2125 0 76 76 3110 1062
2002 Feb 18
29
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 19 Y scaler programming at PAL, input frame size: 640 x 480, half anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 1833066 1833066 1833066 1833066 1833066 1820638 1820638 1820638 1820638 1820638 1805104 1805104 1805104 1805104 1805104 1792676 1792676 1792676 1792676 1792676 1777142 1777142 1777142 1777142 1777142 3254 3254 3254 3254 3254 3277 3277 3277 3277 3277 3305 3305 3305 3305 3305 3328 3328 3328 3328 3328 3354 3354 3354 3354 3354 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 63 67 71 75 79 61 65 69 72 76 59 63 66 70 74 57 60 64 68 71 54 58 61 65 69 63 67 71 75 79 61 65 69 72 76 59 63 66 70 74 57 60 64 68 71 54 58 61 65 69 3673 3673 3673 3673 3673 3686 3686 3686 3686 3686 3698 3698 3698 3698 3698 3711 3711 3711 3711 3711 3724 3724 3724 3724 3724 601 601 601 601 601 614 614 614 614 614 626 626 626 626 626 639 639 639 639 639 652 652 652 652 652
Full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 250 0 41 291 1870348 3108 1890 76 76 3600 607
2002 Feb 18
30
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 20 Y scaler programming at PAL, input frame size: 640 x 480, no anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 1833066 1833066 1833066 1833066 1833066 1820638 1820638 1820638 1820638 1820638 1805104 1805104 1805104 1805104 1805104 1792676 1792676 1792676 1792676 1792676 1777142 1777142 1777142 1777142 1777142 4093 4093 4093 4093 4093 4090 4090 4090 4090 4090 4092 4092 4092 4092 4092 4088 4088 4088 4088 4088 4095 4095 4095 4095 4095 3630 3630 3630 3630 3630 3570 3570 3570 3570 3570 3510 3510 3510 3510 3510 3450 3450 3450 3450 3450 3400 3400 3400 3400 3400 64 67 71 75 79 61 65 69 73 76 59 63 66 70 74 57 60 64 68 71 54 58 62 65 69 64 67 71 75 79 61 65 69 73 76 59 63 66 70 74 57 60 64 68 71 54 58 62 65 69 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4091 4095 4095 4095 4095 4095 228 228 228 228 228 258 258 258 258 258 288 288 288 288 288 318 318 318 318 318 345 345 345 345 345
Full size (horizontal size: 702 pixels) 288 0 0 0 0 0 0 0 0 0 0
Small size (horizontal size: 620 pixels) 250 0 41 291 1870348 4088 3780 76 76 4090 152
2002 Feb 18
31
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 21 Y scaler programming at PAL, input frame size: 800 x 600, full anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 2930917 2930917 2930917 2930917 2930917 2911033 2911033 2911033 2911033 2911033 2887172 2887172 2887172 2887172 2887172 2863311 2863311 2863311 2863311 2863311 2843427 2843427 2843427 2843427 2843427 1736 1736 1736 1736 1736 1749 1749 1749 1749 1749 1763 1763 1763 1763 1763 1778 1778 1778 1778 1778 1790 1790 1790 1790 1790 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 84 89 93 98 77 81 86 91 95 73 78 83 87 92 71 75 80 85 89 68 72 77 82 86 79 84 89 93 98 77 81 86 91 95 73 78 83 87 92 71 75 80 85 89 68 72 77 82 86 2915 2915 2915 2915 2915 2922 2922 2922 2922 2922 2929 2929 2929 2929 2929 2935 2935 2935 2935 2935 2942 2942 2942 2942 2942 867 867 867 867 867 874 874 874 874 874 881 881 881 881 881 887 887 887 887 887 894 894 894 894 894
Full size (horizontal size: 702 pixels) 288 0 22 310 2596864 1960 0 43 43 3027 979
Small size (horizontal size: 620 pixels) 250 0 41 291 2990569 1701 0 95 95 2898 850
2002 Feb 18
32
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 22 Y scaler programming at PAL, input frame size: 800 x 600, half anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 2930917 2930917 2930917 2930917 2930917 2911033 2911033 2911033 2911033 2911033 2887172 2887172 2887172 2887172 2887172 2863311 2863311 2863311 2863311 2863311 2843427 2843427 2843427 2843427 2843427 2604 2604 2604 2604 2604 2625 2625 2625 2625 2625 2645 2645 2645 2645 2645 2666 2666 2666 2666 2666 2686 2686 2686 2686 2686 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 80 84 89 94 98 77 82 86 91 96 74 79 83 88 92 71 75 80 85 89 68 73 77 82 86 80 84 89 94 98 77 82 86 91 96 74 79 83 88 92 71 75 80 85 89 68 73 77 82 86 3349 3349 3349 3349 3349 3359 3359 3359 3359 3359 3369 3369 3369 3369 3369 3379 3379 3379 3379 3379 3390 3390 3390 3390 3390 277 277 277 277 277 287 287 287 287 287 297 297 297 297 297 307 307 307 307 307 318 318 318 318 318
Full size (horizontal size: 702 pixels) 288 0 22 310 2596864 2940 2048 43 43 3517 445
Small size (horizontal size: 620 pixels) 250 0 41 291 2990569 2553 2048 96 96 3323 251
2002 Feb 18
33
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Table 23 Y scaler programming at PAL, input frame size: 800 x 600, no anti-flicker filter TV LINE OFFSET -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 -4 -2 0 2 4 FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE
Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 255 255 255 255 257 257 257 257 257 259 259 259 259 259 261 261 261 261 261 263 263 263 263 263 35 37 39 41 43 34 36 38 40 42 33 35 37 39 41 32 34 36 38 40 31 33 35 37 39 290 292 294 296 298 291 293 295 297 299 292 294 296 298 300 293 295 297 299 301 294 296 298 300 302 2930917 2930917 2930917 2930917 2930917 2911033 2911033 2911033 2911033 2911033 2887172 2887172 2887172 2887172 2887172 2863311 2863311 2863311 2863311 2863311 2843427 2843427 2843427 2843427 2843427 3473 3473 3473 3473 3473 3500 3500 3500 3500 3500 3527 3527 3527 3527 3527 3555 3555 3555 3555 3555 3582 3582 3582 3582 3582 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 4095 80 84 89 94 99 77 82 87 91 96 74 79 83 88 93 71 76 80 85 89 68 73 78 82 87 81 85 90 95 100 78 83 88 92 97 75 80 84 89 94 72 77 81 86 90 69 74 79 83 88 3783 3783 3783 3783 3783 3796 3796 3796 3796 3796 3810 3810 3810 3810 3810 3823 3823 3823 3823 3823 3837 3837 3837 3837 3837 3161 3161 3161 3161 3161 3202 3202 3202 3202 3202 3242 3242 3242 3242 3242 3284 3284 3284 3284 3284 3324 3324 3324 3324 3324
Full size (horizontal size: 702 pixels) 288 0 22 310 2596864 3923 4095 44 45 4007 3836
Small size (horizontal size: 620 pixels) 250 0 41 291 2990569 3405 4095 96 97 3748 3059
2002 Feb 18
34
Philips Semiconductors
Product specification
Digital video encoder
Table 24 "ITU-R BT.601" signal component levels SIGNALS(1) COLOUR Y White Yellow Cyan Green Magenta Red Blue Black Note 1. Transformation: a) R = Y + 1.3707 x (CR - 128) b) G = Y - 0.3365 x (CB - 128) - 0.6982 x (CR - 128) c) B = Y + 1.7324 x (CB - 128). Table 25 Pin assignment for input format 0 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FALLING CLOCK EDGE G3/Y3 G2/Y2 G1/Y1 G0/Y0 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 R2/CR2 R1/CR1 R0/CR0 G7/Y7 G6/Y6 G5/Y5 G4/Y4 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 235 210 170 145 106 81 41 16 CB 128 16 166 54 202 90 240 128 CR 128 146 16 34 222 240 110 128 R 235 235 16 16 235 235 16 16 G 235 235 235 235 16 16 16 16 B 235 16 235 16 235 16 235 16 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PIN
SAA7102; SAA7103
Table 26 Pin assignment for input format 1 5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB FALLING CLOCK EDGE G2 G1 G0 B4 B3 B2 B1 B0 RISING CLOCK EDGE X R4 R3 R2 R1 R0 G4 G3
Table 27 Pin assignment for input format 2 5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB PIN FALLING CLOCK EDGE G2 G1 G0 B4 B3 B2 B1 B0 RISING CLOCK EDGE R4 R3 R2 R1 R0 G5 G4 G3
Table 28 Pin assignment for input format 3 8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR FALLING CLOCK EDGE n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE n Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) FALLING CLOCK EDGE n+1 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE n+1 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
2002 Feb 18
35
Philips Semiconductors
Product specification
Digital video encoder
Table 29 Pin assignment for input format 4 8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-CR (ITU-R BT.656, 27 MHz CLOCK) RISING CLOCK EDGE n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE n+1 Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) RISING CLOCK EDGE n+2 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE n+3 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
SAA7102; SAA7103
Table 31 Pin assignment for input format 6 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FALLING CLOCK EDGE G4/Y4 G3/Y3 G2/Y2 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 G0/Y0 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 G7/Y7 G6/Y6 G5/Y5 R2/CR2 R1/CR1 R0/CR0 G1/Y1
PIN
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Table 30 Pin assignment for input format 5; note 1 8-BIT NON-INTERLACED INDEX COLOUR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Note 1. X = don't care. FALLING CLOCK EDGE X X X X INDEX7 INDEX6 INDEX5 INDEX4 INDEX3 INDEX2 INDEX1 INDEX0 RISING CLOCK EDGE X X X X X X X X X X X X
2002 Feb 18
36
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 7.19 Bit allocation map 2002 Feb 18 2002 Feb 18 37 37 Philips Semiconductors
Digital video encoder Digital video encoder
Table 32 Slave receiver (slave address 88H) REGISTER FUNCTION Status byte (read only) Null Common DAC adjust fine R DAC adjust coarse G DAC adjust coarse B DAC adjust coarse MSM threshold Monitor sense mode Chip ID (02B or 03B, read only) Wide screen signal Wide screen signal Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Gain luminance for RGB Gain colour difference for RGB Input port control 1 VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 Chrominance phase Gain U SUB ADDR. (HEX) 00 01 to 15 16 17 18 19 1A 1B 1C 26 27 28 29 2A 2B 2C 2D 2E to 37 38 39 3A 54 55 56 57 58 59 5A 5B D7 VER2
(1) (1) (1) (1) (1)
D6 VER1
(1) (1) (1) (1) (1)
D5 VER0
(1) (1) (1) (1) (1)
D4 CCRDO
(1) (1)
D3 CCRDE
(1)
D2
(1) (1)
D1 FSEQ
(1)
D0 O_E
(1)
RDACC4 GDACC4 BDACC4 MSMT4
(1)
DACF3 RDACC3 GDACC3 BDACC3 MSMT3
(1)
DACF2 RDACC2 GDACC2 BDACC2 MSMT2 RCOMP CID2 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 CLK2EN
(1)
DACF1 RDACC1 GDACC1 BDACC1 MSMT1 GCOMP CID1 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17
(1) (1)
DACF0 RDACC0 GDACC0 BDACC0 MSMT0 BCOMP CID0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16
(1) (1)
MSMT7 MSM CID7 WSS7 WSSON
(1)
MSMT6
(1)
MSMT5
(1)
CID6 WSS6
(1) (1) (1)
SRES CG07 CG15 CGEN VBSEN
(1) (1) (1)
CG06 CG14
(1)
CID5 WSS5 WSS13 BS5 BE5 CG05 CG13
(1)
CID4 WSS4 WSS12 BS4 BE4 CG04 CG12
(1)
CVBSEN1
(1) (1) (1) (1) (1)
CVBSEN0
(1) (1) (1) (1) (1)
CEN
(1)
CID3 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 ENCOFF
(1)
CBENB VPSEN VPS57 VPS117 VPS127 VPS137 VPS147 CHPS7 GAINU7
GY4 GCD4 SYMP
(1)
GY3 GCD3 DEMOFF
(1)
GY2 GCD2 CSYNC
(1)
GY1 GCD1 Y2C EDGE2 VPS51 VPS111 VPS121 VPS131 VPS141 CHPS1 GAINU1
GY0 GCD0 UV2C EDGE1 VPS50 VPS110 VPS120 VPS130 VPS140 CHPS0 GAINU0
SAA7102; SAA7103 SAA7102; SAA7103
VPS56 VPS116 VPS126 VPS136 VPS146 CHPS6 GAINU6
VPS55 VPS115 VPS125 VPS135 VPS145 CHPS5 GAINU5
VPS54 VPS114 VPS124 VPS134 VPS144 CHPS4 GAINU4
VPS53 VPS113 VPS123 VPS133 VPS143 CHPS3 GAINU3
VPS52 VPS112 VPS122 VPS132 VPS142 CHPS2 GAINU2
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Feb 18 2002 Feb 18 38 38 Philips Semiconductors SUB ADDR. (HEX) 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79
Digital video encoder Digital video encoder
REGISTER FUNCTION Gain V Gain U MSB, black level Gain V MSB, blanking level CCR, blanking level VBI Null Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Null Trigger control Trigger control Multi control Closed Caption, teletext enable Active display window horizontal start Active display window horizontal end MSBs ADWH TTX request horizontal start TTX request horizontal delay CSYNC advance TTX odd request vertical start TTX odd request vertical end TTX even request vertical start TTX even request vertical end
D7 GAINV7 GAINU8 GAINV8 CCRS1
(1)
D6 GAINV6
(1) (1)
D5 GAINV5 BLCKL5 BLNNL5 BLNVB5
(1) (1)
D4 GAINV4 BLCKL4 BLNNL4 BLNVB4
(1)
D3 GAINV3 BLCKL3 BLNNL3 BLNVB3
(1) (1)
D2 GAINV2 BLCKL2 BLNNL2 BLNVB2
(1)
D1 GAINV1 BLCKL1 BLNNL1 BLNVB1
(1)
D0 GAINV0 BLCKL0 BLNNL0 BLNVB0
(1)
CCRS0
(1)
DOWND
(1)
FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17
(1)
DOWNA BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16
(1)
BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15
(1)
YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14
(1)
BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13
(1)
SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12
(1)
PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11
(1)
FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10
(1)
HTRIG7 HTRIG10
(1)
CCEN1 ADWHS7 ADWHE7
(1)
HTRIG6 HTRIG9 BLCKON CCEN0 ADWHS6 ADWHE6 ADWHE10 TTXHS6
(1)
HTRIG5 HTRIG8 PHRES1 TTXEN ADWHS5 ADWHE5 ADWHE9 TTXHS5
(1)
HTRIG4 VTRIG4 PHRES0 SCCLN4 ADWHS4 ADWHE4 ADWHE8 TTXHS4
(1)
HTRIG3 VTRIG3 LDEL1 SCCLN3 ADWHS3 ADWHE3
(1)
HTRIG2 VTRIG2 LDEL0 SCCLN2 ADWHS2 ADWHE2 ADWHS10 TTXHS2 TTXHD2
(1)
HTRIG1 VTRIG1 FLC1 SCCLN1 ADWHS1 ADWHE1 ADWHS9 TTXHS1 TTXHD1
(1)
HTRIG0 VTRIG0 FLC0 SCCLN0 ADWHS0 ADWHE0 ADWHS8 TTXHS0 TTXHD0
(1)
SAA7102; SAA7103 SAA7102; SAA7103
TTXHS7
(1)
CSYNCA4 TTXOVS7 TTXOVE7 TTXEVS7 TTXEVE7
CSYNCA3 CSYNCA2 CSYNCA1 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVE6 TTXOVE5 TTXOVE4 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVE6 TTXEVE5 TTXEVE4
TTXHS3 TTXHD3 CSYNCA0 TTXOVS3 TTXOVE3 TTXEVS3 TTXEVE3
Product specification
TTXOVS2 TTXOVE2 TTXEVS2 TTXEVE2
TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1
TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Feb 18 2002 Feb 18 39 39 Philips Semiconductors SUB ADDR. (HEX) 7A 7B 7C 7D 7E 7F 80 81 82 83 84 to 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2
Digital video encoder Digital video encoder
REGISTER FUNCTION First active line Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line FIFO status (read only) Pixel clock 0 Pixel clock 1 Pixel clock 2 Null Horizontal offset Pixel number Vertical offset odd Vertical offset even MSBs Line number Scaler CTRL, MCB YPIX Sync control Line length Input delay, MSB line length Horizontal increment Vertical increment MSBs vertical and horizontal increment Weighting factor odd Weighting factor even Weighting factor MSB Vertical line skip Blank enable for NI-bypass, vertical line skip MSB Border colour Y
D7 FAL7 LAL7 TTX60
(1)
D6 FAL6 LAL6 LAL8
(1)
D5 FAL5 LAL5
(1) (1)
D4 FAL4 LAL4 FAL8
(1)
D3 FAL3 LAL3 TTXEVE8
(1)
D2 FAL2 LAL2 TTXOVE8
(1)
D1 FAL1 LAL1 TTXEVS8
(1)
D0 FAL0 LAL0 TTXOVS8
(1)
LINE12 LINE20
(1)
LINE11 LINE19
(1)
LINE10 LINE18
(1)
LINE9 LINE17
(1)
LINE8 LINE16
(1)
LINE7 LINE15
(1)
PCL07 PCL15 PCL23
(1)
PCL06 PCL14 PCL22
(1)
PCL05 PCL13 PCL21
(1)
PCL04 PCL12 PCL20
(1)
PCL03 PCL11 PCL19
(1)
PCL02 PCL10 PCL18
(1)
LINE6 LINE14 OVFL PCL01 PCL09 PCL17
(1)
LINE5 LINE13 UDFL PCL00 PCL08 PCL16
(1)
XOFS7 XPIX7 YOFSO7 YOFSE7 YOFSE9 YPIX7 EFS HFS HLEN7 IDEL3 XINC7 YINC7 YINC11
XOFS6 XPIX6 YOFSO6 YOFSE6 YOFSE8 YPIX6 PCBN VFS HLEN6 IDEL2 XINC6 YINC6 YINC10
XOFS5 XPIX5 YOFSO5 YOFSE5 YOFSO9 YPIX5 SLAVE OFS HLEN5 IDEL1 XINC5 YINC5 YINC9
XOFS4 XPIX4 YOFSO4 YOFSE4 YOFSO8 YPIX4 ILC PFS HLEN4 IDEL0 XINC4 YINC4 YINC8
XOFS3 XPIX3 YOFSO3 YOFSE3 XPIX9 YPIX3 YFIL OVS HLEN3
(1)
XINC3 YINC3 XINC11
XOFS2 XPIX2 YOFSO2 YOFSE2 XPIX8 YPIX2 HSL PVS HLEN2 HLEN10 XINC2 YINC2 XINC10
XOFS1 XPIX1 YOFSO1 YOFSE1 XOFS9 YPIX1 YPIX9 OHS HLEN1 HLEN9 XINC1 YINC1 XINC9
XOFS0 XPIX0 YOFSO0 YOFSE0 XOFS8 YPIX0 YPIX8 PHS HLEN0 HLEN8 XINC0 YINC0 XINC8 YIWGTO0 YIWGTE0 YIWGTO8 YSKIP0 YSKIP8 BCY0
SAA7102; SAA7103 SAA7102; SAA7103
YIWGTO7 YIWGTO6 YIWGTO5 YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE11 YIWGTE10 YIWGTE9 YSKIP7 YSKIP6 YSKIP5 (1) (1) BLEN BCY7 BCY6 BCY5
YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9 YSKIP4 YSKIP3 YSKIP2 YSKIP1 (1) YSKIP11 YSKIP10 YSKIP9 BCY4 BCY3 BCY2 BCY1
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Feb 18 2002 Feb 18 40 40 Philips Semiconductors SUB ADDR. (HEX) A3 A4 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
Digital video encoder Digital video encoder
REGISTER FUNCTION Border colour U Border colour V Cursor colour 1 R Cursor colour 1 G Cursor colour 1 B Cursor colour 2 R Cursor colour 2 G Cursor colour 2 B Auxiliary cursor colour R Auxiliary cursor colour G Auxiliary cursor colour B Horizontal cursor position Horizontal hot spot, MSB XCP Vertical cursor position Vertical hot spot, MSB YCP Input path control Cursor bit map Colour look-up table Note
D7 BCU7 BCV7 CC1R7 CC1G7 CC1B7 CC2R7 CC2G7 CC2B7 AUXR7 AUXG7 AUXB7 XCP7 XHS4 YCP7 YHS4 LUTOFF
D6 BCU6 BCV6 CC1R6 CC1G6 CC1B6 CC2R6 CC2G6 CC2B6 AUXR6 AUXG6 AUXB6 XCP6 XHS3 YCP6 YHS3 CMODE
D5 BCU5 BCV5 CC1R5 CC1G5 CC1B5 CC2R5 CC2G5 CC2B5 AUXR5 AUXG5 AUXB5 XCP5 XHS2 YCP5 YHS2 LUTL
D4 BCU4 BCV4 CC1R4 CC1G4
D3 BCU3 BCV3 CC1R3 CC1G3
D2 BCU2 BCV2 CC1R2 CC1G2 CC1B2 CC2R2 CC2G2 CC2B2 AUXR2 AUXG2 AUXB2 XCP2 XCP10 YCP2
(1)
D1 BCU1 BCV1 CC1R1 CC1G1 CC1B1 CC2R1 CC2G1 CC2B1 AUXR1 AUXG1 AUXB1 XCP1 XCP9 YCP1 YCP9 MATOFF
D0 BCU0 BCV0 CC1R0 CC1G0 CC1B0 CC2R0 CC2G0 CC2B0 AUXR0 AUXG0 AUXB0 XCP0 XCP8 YCP0 YCP8 DFOFF
CC1B4 CC1B3 CC2R4 CC2R3 CC2G4 CC2G3 CC2B4 CC2B3 AUXR4 AUXR3 AUXG4 AUXG3 AUXB4 AUXB3 XCP4 XCP3 XHS1 XHS0 YCP4 YCP3 YHS1 YHS0 IF2 IF1 RAM address (see Table 106) RAM address (see Table 107)
IF0
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
SAA7102; SAA7103 SAA7102; SAA7103
Product specification
Philips Semiconductors
Product specification
Digital video encoder
7.20 I2C-bus format
SAA7102; SAA7103
Table 33 I2C-bus write access to control registers; see Table 38 S 1 0 0 0 1 0 0 0 A SUBADDRESS A DATA 0 A -------DATA n A P
Table 34 I2C-bus write access to cursor bit map (subaddress FEH); see Table 38 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A DATA 0 A -------DATA n A P
Table 35 I2C-bus write access to colour look-up table (subaddress FFH); see Table 38 S 1 0 0 0 1 0 0 0 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A -------P
Table 36 I2C-bus read access to control registers; see Table 38 S 1 0 0 0 1 0 0 0 A SUBADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------DATA n Am P
Table 37 I2C-bus read access to cursor bit map or colour LUT; see Table 38 S 1 0 0 0 1 0 0 0 A FEH or FFH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P
Table 38 Explanations of Tables 33 to 37 CODE S Sr 1 0 0 0 1 0 0 X; note 1 A Am SUBADDRESS; note 2 DATA -------P RAM ADDRESS Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. START condition repeated START condition slave address acknowledge generated by the slave acknowledge generated by the master subaddress byte data byte continued data bytes and acknowledges STOP condition start address for RAM access DESCRIPTION
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
7.21 Slave receiver
SAA7102; SAA7103
Table 39 Subaddress 16H DATA BYTE DACF DESCRIPTION output level adjustment fine in 1% steps for all DACs; default after reset is 00H; see Table 40
Table 40 Fine adjustment of DAC output voltage BINARY 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 Table 41 Subaddresses 17H to 19H DATA BYTE RDACC GDACC BDACC DESCRIPTION output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion GAIN (%) 7 6 5 4 3 2 1 0 0 -1 -2 -3 -4 -5 -6 -7
Table 42 Subaddress 1AH DATA BYTE MSMT DESCRIPTION monitor sense mode threshold for DAC output voltage, should be set to 70
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
Table 43 Subaddress 1BH DATA BYTE MSM RCOMP (read only) GCOMP (read only) BCOMP (read only) LOGIC LEVEL 0 1 0 1 0 1 0 1 monitor sense mode on DESCRIPTION
SAA7102; SAA7103
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset check comparator at DAC on pin RED_CR_C is active, output is loaded check comparator at DAC on pin RED_CR_C is inactive, output is not loaded check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
Table 44 Subaddresses 26H and 27H DATA BYTE WSS LOGIC LEVEL - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 1 wide screen signalling output is disabled; default after reset wide screen signalling output is enabled DESCRIPTION
Table 45 Subaddress 28H DATA BYTE BS LOGIC LEVEL - DESCRIPTION starting point of burst in clock cycles REMARKS PAL: BS = 33 (21H); default after reset if strapping pin 13 tied to HIGH NTSC: BS = 25 (19H); default after reset if strapping pin 13 tied to LOW Table 46 Subaddress 29H DATA BYTE SRES LOGIC LEVEL 0 1 BE - DESCRIPTION pin TTX_SRES accepts a teletext bit stream (TTX) pin TTX_SRES accepts a sync reset input (SRES) ending point of burst in clock cycles default after reset a HIGH impulse resets synchronization of the encoder (first field, first line) PAL: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to HIGH NTSC: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to LOW REMARKS
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Philips Semiconductors
Product specification
Digital video encoder
Table 47 Subaddresses 2AH to 2CH DATA BYTE CG LOGIC LEVEL - DESCRIPTION
SAA7102; SAA7103
LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. copy generation data output is disabled; default after reset copy generation data output is enabled
CGEN
0 1
Table 48 Subaddress 2DH DATA BYTE VBSEN LOGIC LEVEL 0 1 CVBSEN1 0 1 CVBSEN0 CEN 0 1 0 1 ENCOFF CLK2EN 0 1 0 1 DESCRIPTION pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal (CVBSEN1 = 1) pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal; default after reset pin GREEN_VBS_CVBS provides a CVBS signal pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (CB) signal pin BLUE_CB_CVBS provides a CVBS signal; default after reset pin RED_CR_C provides a component RED (R) or colour difference RED (CR) signal pin RED_CR_C provides a chrominance signal (C) as modulated subcarrier for S-video; default after reset encoder is active; default after reset encoder bypass, DACs are provided with RGB signal after cursor insertion block pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ) pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default after reset
Table 49 Subaddresses 38H and 39H DATA BYTE GY4 to GY0 GCD4 to GCD0 DESCRIPTION Gain luminance of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application. Gain colour difference of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application.
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Philips Semiconductors
Product specification
Digital video encoder
Table 50 Subaddress 3AH DATA BYTE CBENB SYMP LOGIC LEVEL 0 1 0 1 DEMOFF CSYNC Y2C UV2C 0 1 0 1 0 1 0 1 data from input ports is encoded colour bar with fixed colours is encoded DESCRIPTION
SAA7102; SAA7103
horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default after reset horizontal and vertical trigger is decoded out of "ITU-R BT.656" compatible data at PD port Y-CB-CR to RGB dematrix is active; default after reset Y-CB-CR to RGB dematrix is bypassed pin 26 provides a horizontal sync for non-interlaced VGA components output (at PIXCLK) pin 26 provides a composite sync for interlaced components output (at XTAL clock) input luminance data is twos complement from PD input port input luminance data is straight binary from PD input port; default after reset input colour difference data is twos complement from PD input port input colour difference data is straight binary from PD input port; default after reset
Table 51 Subaddress 54H DATA BYTE VPSEN EDGE2 LOGIC LEVEL 0 1 0 1 EDGE1 0 1 DESCRIPTION video programming system data insertion is disabled; default after reset video programming system data insertion in line 16 is enabled internal PPD2 data is sampled on the rising clock edge internal PPD2 data is sampled on the falling clock edge; see Tables 25 to 30; default after reset internal PPD1 data is sampled on the rising clock edge; see Tables 25 to 30; default after reset internal PPD1 data is sampled on the falling clock edge
Table 52 Subaddresses 55H to 59H DATA BYTE VPS5 VPS11 VPS12 VPS13 VPS14 DESCRIPTION fifth byte of video programming system data eleventh byte of video programming system data twelfth byte of video programming system data thirteenth byte of video programming system data fourteenth byte of video programming system data REMARKS in line 16; LSB first; all other bytes are not relevant for VPS
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Philips Semiconductors
Product specification
Digital video encoder
Table 53 Subaddress 5AH; note 1 DATA BYTE CHPS DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees VALUE 6BH 16H 25H 46H Note 1. The default after reset is 00H. Table 54 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76H) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7DH) Table 55 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 IRE GAINV = 0 GAINV = 175 (AFH) Table 56 Subaddress 5DH DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-sync = 140 IRE; note 1 BLCKL = 0; note 1 white-to-sync = 143 IRE; note 2 BLCKL = 0; note 2
SAA7102; SAA7103
RESULT PAL B/G and data from input ports in master mode PAL B/G and data from look-up table NTSC M and data from input ports in master mode NTSC M and data from look-up table
REMARKS GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
REMARKS GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal
REMARKS recommended value: BLCKL = 58 (3AH) output black level = 29 IRE recommended value: BLCKL = 51 (33H) output black level = 27 IRE
BLCKL = 63 (3FH); note 1 output black level = 49 IRE
BLCKL = 63 (3FH); note 2 output black level = 47 IRE Notes 1. Output black level/IRE = BLCKL x 2/6.29 + 28.9. 2. Output black level/IRE = BLCKL x 2/6.18 + 26.5.
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Philips Semiconductors
Product specification
Digital video encoder
Table 57 Subaddress 5EH DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE; note 1 BLNNL = 0; note 1 BLNNL = 63 (3FH); note 1 white-to-sync = 143 IRE; note 2 BLNNL = 0; note 2 BLNNL = 63 (3FH); note 2 Notes 1. Output black level/IRE = BLNNL x 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL x 2/6.18 + 25.9; default after reset: 35H. Table 58 Subaddress 5FH DATA BYTE CCRS BLNVB DESCRIPTION select cross-colour reduction filter in luminance; see Table 59
SAA7102; SAA7103
REMARKS recommended value: BLNNL = 46 (2EH) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35H) output blanking level = 26 IRE output blanking level = 46 IRE
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
Table 59 Logic levels and function of CCRS CCRS1 0 0 1 1 CCRS0 0 1 0 1 DESCRIPTION no cross-colour reduction; for overall transfer characteristic of luminance see Fig.6 cross-colour reduction #1 active; for overall transfer characteristic see Fig.6 cross-colour reduction #2 active; for overall transfer characteristic see Fig.6 cross-colour reduction #3 active; for overall transfer characteristic see Fig.6
Table 60 Subaddress 61H DATA BYTE DOWND DOWNA YGS SCBW LOGIC LEVEL 0 1 0 1 0 1 0 1 PAL FISE 0 1 0 1 DESCRIPTION digital core in normal operational mode; default after reset digital core in sleep mode and is reactivated with an I2C-bus address DACs in normal operational mode; default after reset DACs in Power-down mode luminance gain for white - black 100 IRE luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 4 and 5) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 4 and 5); default after reset NTSC encoding (non-alternating V component) PAL encoding (alternating V component) 864 total pixel clocks per line 858 total pixel clocks per line 47
2002 Feb 18
Philips Semiconductors
Product specification
Digital video encoder
Table 61 Subaddress 62H DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.90 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 x nominal Table 62 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE FSC0 to FSC3 DESCRIPTION ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) CONDITIONS
SAA7102; SAA7103
REMARKS recommended value: BSTA = 63 (3FH) recommended value: BSTA = 45 (2DH) recommended value: BSTA = 67 (43H) recommended value: BSTA = 47 (2FH); default after reset
REMARKS
FSC3 = most significant byte; f fsc 32 FSC = round ------- x 2 ; note 1 FSC0 = least significant byte f llc
Note 1. Examples: a) NTSC M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). Table 63 Subaddresses 67H to 6AH DATA BYTE L21O0 L21O1 L21E0 L21E1 DESCRIPTION first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format.
Table 64 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; the default value is 0
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Philips Semiconductors
Product specification
Digital video encoder
Table 65 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to chip-internal vertical input
SAA7102; SAA7103
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH); the default value is 0 Table 66 Subaddress 6EH DATA BYTE BLCKON PHRES LDEL FLC LOGIC LEVEL 0 1 - - - DESCRIPTION encoder in normal operation mode; default after reset output signal is forced to blanking level selects the phase reset mode of the colour subcarrier generator; see Table 67 selects the delay on luminance path with reference to chrominance path; see Table 68 field length control; see Table 69
Table 67 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no subcarrier reset subcarrier reset every two lines subcarrier reset every eight fields subcarrier reset every four fields
Table 68 Logic levels and function of LDEL DATA BYTE DESCRIPTION LDEL1 0 0 1 1 LDEL0 0 1 0 1 no luminance delay; default after reset 1 LLC luminance delay 2 LLC luminance delay 3 LLC luminance delay
Table 69 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 0 0 1 1 FLC0 0 1 0 1 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
2002 Feb 18
49
Philips Semiconductors
Product specification
Digital video encoder
Table 70 Subaddress 6FH DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - DESCRIPTION enables individual line 21 encoding; see Table 71 disables teletext insertion; default after reset enables teletext insertion
SAA7102; SAA7103
selects the actual line, where Closed Caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 71 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding off; default after reset enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
Table 72 Subaddresses 70H to 72H DATA BYTE ADWHS DESCRIPTION active display window horizontal start; defines the start of the active TV display portion after the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed ADWHE active display window horizontal end; defines the end of the active TV display portion before the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed Table 73 Subaddress 73H DATA BYTE TTXHS DESCRIPTION start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see Fig.14 REMARKS TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC Table 74 Subaddress 74H DATA BYTE TTXHD DESCRIPTION indicates the delay in clock cycles between rising edge of TTXRQ output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at pin TTX_SRES REMARKS minimum value: TTXHD = 2; is default after reset
Table 75 Subaddress 75H DATA BYTE CSYNCA 2002 Feb 18 DESCRIPTION advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks 50
Philips Semiconductors
Product specification
Digital video encoder
Table 76 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems Table 77 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems Table 78 Subaddresses 7AH to 7CH DATA BYTE FAL LAL DESCRIPTION
SAA7102; SAA7103
REMARKS TTXOVS = 05H; is default after reset if strapped to PAL TTXOVS = 06H; is default after reset if strapped to NTSC TTXOVE = 16H; is default after reset if strapped to PAL TTXOVE = 10H; is default after reset if strapped to NTSC
REMARKS TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC
first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems and LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse
Table 79 Subaddress 7CH DATA BYTE TTX60 LOGIC LEVEL 0 1 DESCRIPTION enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset enables world standard teletext 60 Hz (FISE = 1)
Table 80 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
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Philips Semiconductors
Product specification
Digital video encoder
Table 81 Subaddresses 81H to 83H DATA BYTE PCL DESCRIPTION
SAA7102; SAA7103
defines the frequency of the synthesized pixel clock PIXCLKO; PCL f PIXCLK = ---------- x f XTAL x 8 ; fXTAL = 27 MHz nominal, e.g. 640 x 480 to NTSC M: PCL = 20F63BH; 24 2 640 x 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
Table 82 Subaddresses 90H and 94H DATA BYTE XOFS DESCRIPTION horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output
Table 83 Subaddresses 91H and 94H DATA BYTE XPIX DESCRIPTION pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses)
Table 84 Subaddresses 92H and 94H DATA BYTE YOFSO DESCRIPTION vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
Table 85 Subaddresses 93H and 94H DATA BYTE YOFSE DESCRIPTION vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 86 Subaddresses 95H and 96H DATA BYTE YPIX DESCRIPTION defines the number of requested input lines from the feeding device; number of requested lines = YPIX + YOFSE - YOFSO
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Philips Semiconductors
Product specification
Digital video encoder
Table 87 Subaddress 96H DATA BYTE EFS PCBN SLAVE ILC YFIL HSL LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 0 1 DESCRIPTION
SAA7102; SAA7103
frame sync signal at pin FSVGC ignored in slave mode frame sync signal at pin FSVGC accepted in slave mode normal polarity of CBO signal (HIGH during active video) inverted polarity of CBO signal (LOW during active video) the SAA7102; SAA7103 is timing master to the graphics controller the SAA7102; SAA7103 is timing slave to the graphics controller if hardware cursor insertion is active, set LOW for non-interlaced input signals if hardware cursor insertion is active, set HIGH for interlaced input signals luminance sharpness booster disabled luminance sharpness booster enabled normal trigger event handling of the horizontal state machine, if the SAA7102; SAA7103 is slave to HSVGC input trigger event for horizontal state machine is shifted 128 PIXCLKs in advance, adapted to a late HSVGC in slave mode
Table 88 Subaddress 97H DATA BYTE HFS LOGIC LEVEL 0 1 VFS 0 1 OFS PFS 0 1 0 1 OVS PVS 0 1 0 1 DESCRIPTION horizontal sync is directly derived from input signal (slave mode) at pin HSVGC horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) vertical sync (field sync) is directly derived from input signal (slave mode) at pin VSVGC vertical sync (field sync) is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) pin FSVGC is switched to input pin FSVGC is switched to active output polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode pin VSVGC is switched to input pin VSVGC is switched to active output polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
DATA BYTE OHS PHS
LOGIC LEVEL 0 1 0 1 pin HSVGC is switched to input
DESCRIPTION
pin HSVGC is switched to active output polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode
Table 89 Subaddresses 98H and 99H DATA BYTE HLEN DESCRIPTION number of PIXCLKs horizontal length; HLEN = ---------------------------------------------------- - 1 line
Table 90 Subaddress 99H DATA BYTE IDEL DESCRIPTION input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel
Table 91 Subaddresses 9AH and 9CH DATA BYTE XINC DESCRIPTION number of output pixels ------------------------------------------------------------line incremental fraction of the horizontal scaling engine; XINC = ------------------------------------------------------------- x 4096 number of input pixels --------------------------------------------------------line
Table 92 Subaddresses 9BH and 9CH DATA BYTE YINC DESCRIPTION number of active output lines incremental fraction of the vertical scaling engine; YINC = --------------------------------------------------------------------------- x 4096 number of active input lines
Table 93 Subaddresses 9DH and 9FH DATA BYTE YIWGTO DESCRIPTION YINC weighting factor for the first line of the odd field; YIWGTO = ------------- + 2048 2
Table 94 Subaddresses 9EH and 9FH DATA BYTE YIWGTE DESCRIPTION YINC - YSKIP weighting factor for the first line of the even field; YIWGTE = ------------------------------------2
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Philips Semiconductors
Product specification
Digital video encoder
Table 95 Subaddresses A0H and A1H DATA BYTE YSKIP DESCRIPTION
SAA7102; SAA7103
vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective; YSKIP = 4095: anti-flicker filter switched off
Table 96 Subaddress A1H DATA BYTE BLEN LOGIC LEVEL 0 1 DESCRIPTION no internal blanking for non-interlaced graphics in bypass mode; default after reset forced internal blanking for non-interlaced graphics in bypass mode
Table 97 Subaddresses A2H to A4H DATA BYTE BCY, BCU and BCV DESCRIPTION luminance and colour difference portion of border colour in underscan area
Table 98 Subaddresses F0H to F2H DATA BYTE CC1R, CC1G and CC1B DESCRIPTION RED, GREEN and BLUE portion of first cursor colour
Table 99 Subaddresses F3H to F5H DATA BYTE CC2R, CC2G and CC2B DESCRIPTION RED, GREEN and BLUE portion of second cursor colour
Table 100 Subaddresses F6H to F8H DATA BYTE AUXR, AUXG and AUXB DESCRIPTION RED, GREEN and BLUE portion of auxiliary cursor colour
Table 101 Subaddresses F9H and FAH DATA BYTE XCP horizontal cursor position DESCRIPTION
Table 102 Subaddress FAH DATA BYTE XHS horizontal hot spot of cursor DESCRIPTION
Table 103 Subaddresses FBH and FCH DATA BYTE YCP vertical cursor position DESCRIPTION
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Philips Semiconductors
Product specification
Digital video encoder
Table 104 Subaddress FCH DATA BYTE YHS vertical hot spot of cursor DESCRIPTION
SAA7102; SAA7103
Table 105 Subaddress FDH DATA BYTE LUTOFF CMODE LUTL IF LOGIC LEVEL 0 1 0 1 0 1 0 1 2 3 4 5 6 MATOFF DFOFF 0 1 0 1 colour look-up table is active colour look-up table is bypassed cursor mode; input colour will be inverted auxiliary cursor colour will be inserted LUT loading via input data stream is inactive colour and cursor LUTs are loaded via input data stream input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR input format is 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB input format is 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB input format is 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR input format is 8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock) (in subaddresses 91H and 94H set XPIX = number of active pixels/line) input format is 8-bit non-interlaced index colour input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering) RGB to CR-Y-CB matrix is active RGB to CR-Y-CB matrix is bypassed down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active down formatter is bypassed DESCRIPTION
Table 106 Subaddress FEH DATA BYTE CURSA DESCRIPTION RAM start address for cursor bit map; the byte following subaddress FEH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
Table 107 Subaddress FFH DATA BYTE COLSA DESCRIPTION RAM start address for colour LUT; the byte following subaddress FFH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up.
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Philips Semiconductors
Product specification
Digital video encoder
7.22 Slave transmitter
SAA7102; SAA7103
Table 108 Slave transmitter (slave address 89H) REGISTER FUNCTION Status byte Chip ID FIFO status DATA BYTE SUBADDRESS D7 00H 1CH 80H VER2 CID7 0 D6 VER1 CID6 0 D5 VER0 CID5 0 D4 CCRDO CID4 0 D3 CCRDE CID3 0 D2 0 CID2 0 D1 FSEQ CID1 OVFL D0 O_E CID0 UDFL
Table 109 Subaddress 00H DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ O_E 1 0 1 0 Table 110 Subaddress 1CH DATA BYTE CID DESCRIPTION chip ID of SAA7102 = 02H; chip ID of SAA7103 = 03H DESCRIPTION version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 010 binary Closed Caption bytes of the odd field have been encoded the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded Closed Caption bytes of the even field have been encoded the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) not first field of a sequence during even field during odd field
Table 111 Subaddress 80H DATA BYTE OVFL UDFL LOGIC LEVEL 0 1 0 1 no FIFO overflow FIFO overflow has occurred; this bit is reset after this subaddress has been read no FIFO underflow FIFO underflow has occurred; this bit is reset after this subaddress has been read DESCRIPTION
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.4 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.5 Chrominance transfer characteristic 2.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) (1) (2) (3) (4) CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. 14
(4) (2) (3) (1)
6
MGD672
Fig.6 Luminance transfer characteristic 1 (excluding scaler).
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.7 Luminance transfer characteristic 2 (excluding scaler).
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB708
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.8 Luminance transfer characteristic in RGB (excluding scaler).
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB706
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.9 Colour difference transfer characteristic in RGB (excluding scaler).
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Philips Semiconductors
Product specification
Digital video encoder
8 BOUNDARY SCAN TEST
SAA7102; SAA7103
The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 112. Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) of the SAA7102; SAA7103 is available on request.
The SAA7102; SAA7103 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7102; SAA7103 follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).
Table 112 BST instructions supported by the SAA7102; SAA7103 INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no support for customer available). This private instruction allows testing by the manufacturer (no support for customer available). When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.10.
CLAMP IDCODE INTEST USER1 8.1
Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 8.2 Device identification codes
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
handbook, full pagewidth
MSB 31 TDI 28 27 0111000100000010 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1
LSB 0 1 TDO
0010
4-bit version code
MHB909
a. SAA7102.
MSB 31 TDI 28 27 0111000100000011 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1 1 LSB 0 TDO
handbook, full pagewidth
0010
4-bit version code
MHB910
b. SAA7103. Fig.10 32 bits of identification code.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and all supply pins connected together. SYMBOL VDDD VDDA Vo(A) Vi(D) Vo(D) VSS Tstg Tamb Vesd Notes 1. Except pin XTALI. 2. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 64 UNIT K/W PARAMETER digital supply voltage analog supply voltage output voltage at analog outputs input voltage at digital inputs and outputs output voltage at digital outputs voltage difference between VSSA(n) and VSSD(n) storage temperature ambient temperature electrostatic discharge voltage all pins note 2 CONDITIONS MIN. -0.5 -0.5 -0.5 outputs in 3-state; -0.5 note 1 outputs active -0.5 - -65 0 MAX. +4.6 +4.6 VDDA + 0.5 +5.5 VDDD + 0.5 100 +150 70 V V V V V mV C C V UNIT
-2000 +2000
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Philips Semiconductors
Product specification
Digital video encoder
11 CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA IDDD Inputs VIL VIH ILI Ci LOW-level input voltage at all digital input pins except pins SDA and SCL HIGH-level input voltage at all digital input pins except pins SDA and SCL input leakage current input capacitance clocks data I/Os at high-impedance Outputs; all digital output pins except pin SDA VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 2 mA IOH = -2 mA - 2.4 -0.5 Vi = LOW or HIGH IOL = 3 mA during acknowledge -10 - 3 -0.5 2.0 - - - - analog supply voltage digital supply voltage analog supply current digital supply current note 1 VDDD = 3.3 V; note 2 3.15 3.0 1 1 PARAMETER CONDITIONS MIN.
SAA7102; SAA7103
TYP.
MAX.
UNIT
3.3 3.3 110 70 - - - - - -
3.45 3.6 140 90
V V mA mA
+0.8 VDDD + 0.3 10 10 8 8
V V A pF pF pF
- - - - - - - - 50 50 - - - - 27 -
0.4 -
V V
I2C-bus; pins SDA and SCL VIL VIH Ii VOL Io TPIXCLK td(CLKD) tr tf Input timing tSU;DAT tHD;DAT fnom f/fnom input data set-up time input data hold time 5 0 - note 5 -50 - - - +50 ns ns LOW-level input voltage HIGH-level input voltage input current LOW-level output voltage (pin SDA) output current 0.3VDDD VDDD + 0.3 +10 0.4 - 100 - 60 60 3 3 V V A V mA 0.7VDDD -
Clock timing; pins PIXCLKI and PIXCLKO cycle time delay from PIXCLKO to PIXCLKI duty factor tHIGH/TPIXCLK duty factor tHIGH/TCLKO2 rise time fall time note 3 note 4 note 3 output note 3 note 3 22.5 - 40 40 - - ns ns % % ns ns
Crystal oscillator nominal frequency permissible deviation of nominal frequency MHz 10-6
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
SYMBOL CRYSTAL SPECIFICATION Tamb CL RS C1 C0 Co(L) to(h) to(d)
PARAMETER
CONDITIONS
MIN. - - -
TYP.
MAX.
UNIT C pF fF pF
ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical)
0 8 - 1.2 2.8
70 - 80 1.8 4.2
1.5 3.5 - - - 1.23 1.0 0.89 0.7 2 37.5 - - -
Data and reference signal output timing output load capacitance output hold time output delay time 8 2 - see Table 113 see Table 113 see Table 113 see Table 113 - - - - - - -3 dB 15 - - 40 - 16 - - - - - - - 3 1 pF ns ns
CVBS and RGB outputs Vo(CVBS)(p-p) output voltage CVBS (peak-to-peak value) Vo(VBS)(p-p) Vo(C)(p-p) Vo(RGB)(p-p) Vo Ro(L) BDAC ILElf(DAC) DLElf(DAC) Notes 1. Minimum value for I2C-bus bit DOWNA = 1. 2. Minimum value for I2C-bus bit DOWND = 1. 3. The data is for both input and output direction. 4. This parameter is arbitrary, if PIXCLKI is looped through the VGC. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. output voltage VBS (S-video) (peak-to-peak value) output voltage C (S-video) (peak-to-peak value) output voltage R, G, B (peak-to-peak value) inequality of output signal voltages output load resistance output signal bandwidth of DACs low frequency integral linearity error of DACs low frequency differential linearity error of DACs V V V V % MHz LSB LSB
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
handbook, full pagewidth
TPIXCLK tHIGH 2.4 V 1.5 V 0.4 V td(CLKD) tf tr 2.0 V
PIXCLKO
PIXCLKI
1.5 V 0.8 V tHD;DAT tSU;DAT tHD;DAT tSU;DAT 2.0 V
PDn 0.8 V to(d) to(h) any output 0.4 V
MHB904
2.4 V
Fig.11 Input/output timing specification.
handbook, full pagewidth
HSVGC
CBO
PD XOFS IDEL XPIX HLEN
MHB905
Fig.12 Horizontal input timing.
2002 Feb 18
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Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
handbook, full pagewidth
HSVGC
VSVGC
CBO YOFS YPIX
MHB906
Fig.13 Vertical input timing.
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Philips Semiconductors
Product specification
Digital video encoder
11.1 Teletext timing
SAA7102; SAA7103
Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct I2C-bus register settings.
Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse.
handbook, full pagewidth
CVBS/Y t TTX text bit #: TTX_SRES t PD TTXRQ_XCLKO2
MHB891
t i(TTXW) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
t FD
Fig.14 Teletext timing.
2002 Feb 18
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dbook, full pagewidth
BST0
BST1
BST2
VDDD1
VDDD2
VDDA2
VDDA1
TMS
TDI
TDO
TCK
TRST
SCL
SDA
PIXCLKO
PIXCLKI
RESET
VSSD2
VSSD1
VSSA1
DUMP
TP3 XCLKO2
RSET
2002 Feb 18 2002 Feb 18
PD [0:11] TP5 HSVGC TP4 CBO HSVGC VSVGC FSVGC CBO
12 APPLICATION INFORMATION
Philips Semiconductors
Digital video encoder Digital video encoder
BST [0:2] TDI TDO SCL SDA 37 11 12 R10 75 AGND R11 75 AGND R12 75 AGND FLTR [0:2] RED_CR_C 27 28 30 25 26 Y1 XTALO XTALI 34 35 VDD3_0 R2 27 MHz C8 10 pF L1 10 H C7 10 pF C9 1 nF FLTR0 FLTR1 FLTR2
VDDA3_2 VDDA3_1 VDD3_2 VDD3_1 10 40 36 29
6 38 7 8
PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
4 3 2 1 44 43 42 41 16 17 18 19
PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
GREEN_VBS_CVBS BLUE_CB_CVBS VSM
VSM HSM_CSYNC
SAA7102H SAA7103H
HSM_CSYNC
22 14
HSVGC VSVGC
69 69
13 FSVGC 21 CBO
TTX_SRES TTXRQ_XCLKO2
23 24
TTX_SRES TTXRQ_XCLKO2
4.7 k S1 CP1 22 F JP9 RESET DGND RESET
DGND
33
39 9
32 31
15
20
5
SAA7102; SAA7103 SAA7102; SAA7103
VDDA3_1 VDDA3_2 C1 100 nF C4 100 nF R3 0 AGND
VDD3_1 VDD3_2 C2 100 nF C3 100 nF
AGND
DGND R9 12 R8 1 k AGND JP10 CLK SHORT R7 22 R6 22
RESET PIXCLKO
Product specification
PIXCLKI
MHB913
DGND
Fig.15 Application circuit.
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
handbook, halfpage
C16 120 pF L2 2.7 H C10 390 pF L3 2.7 H C13 560 pF
AGND
JP11 FIN
JP12 FOUT
FILTER 1 = byp. ll act.
MHB912
Fig.16 FLTR0, FLTR1 and FLTR2 of Fig.15.
12.1
Analog output voltages
The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in Tables 54 to 61 for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 113 for a 100100 colour bar signal. Table 113 Digital output signals conversion range SET/OUT Digital settings Digital output Analog settings Analog output 12.2
By setting the reference currents of the DACs as shown in Table 113, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16H, parameter DACF = 0000b, that means the fine adjustment for all DACs in common is set to 0%. If S-video output is desired, the adjustment for the C (chrominance subcarrier) output should be identical to the one for VBS (luminance plus sync) output.
CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE see Tables 54 to 61 1014 e.g. B DAC = 1FH 1.23 V (p-p) see Tables 54 to 61 881 e.g. G DAC = 1BH 1.00 V (p-p)
RGB, BLACK-TO-WHITE see Table 49 876 e.g. R DAC = G DAC = B DAC = 0BH 0.70 V (p-p)
Suggestions for a board layout
Use separate ground planes for analog and digital ground. Connect these planes only at one point directly under the device, by using a 0 resistor directly at the supply stage. Use separate supply lines for the analog and digital supply. Place the supply decoupling capacitors close to the supply pins. Use Lbead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (EMC).
Place the analog coupling (clamp) capacitors close to the analog input pins. Place the analog termination resistors close to the coupling capacitors. Be careful of hidden layout capacitors around the crystal application. Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy.
2002 Feb 18
70
Philips Semiconductors
Product specification
Digital video encoder
13 PACKAGE OUTLINES BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm
D D1 B A
SAA7102; SAA7103
SOT472-1
ball A1 index area A E1 E A1 detail X A2
k
k e1 e P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.75 A1 0.5 0.3 A2 1.25 1.05 b 0.6 0.4 D 15.2 14.8 D1 13.7 13.0 E 15.2 14.8 E1 13.7 13.0 e 1.0 e1 13.0 k 1.65 1.10 v 0.3 w 0.1 y 0.15 y1 0.35 5 scale 10 mm X vMB b
w M
C y1 C y
vMA
e
e1
OUTLINE VERSION SOT472-1
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-12-02 00-03-04
2002 Feb 18
71
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
2002 Feb 18
72
Philips Semiconductors
Product specification
Digital video encoder
14 SOLDERING 14.1 Introduction to soldering surface mount packages
SAA7102; SAA7103
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Feb 18
73
Philips Semiconductors
Product specification
Digital video encoder
14.5
SAA7102; SAA7103
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE REFLOW(1) suitable suitable suitable suitable suitable
BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 15 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2002 Feb 18
74
Philips Semiconductors
Product specification
Digital video encoder
16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 PURCHASE OF PHILIPS I2C COMPONENTS 17 DISCLAIMERS
SAA7102; SAA7103
Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Feb 18
75
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/02/pp76
Date of release: 2002
Feb 18
Document order number:
9397 750 09214

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